This application claims the benefit of priority of Korean Patent Application No. P994372 filed on Feb. 9, 1999, which application is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
This invention relates to a circuit for driving an active matrix type display device of, and more particularly to a shift register for driving pixel rows in a liquid crystal display.
2. Discussion of the Related Art
Generally, a conventional liquid crystal display device used in a television or a computer includes a liquid crystal matrix having liquid crystal cells arranged at intersections of data lines with select or gate lines. The select lines are horizontal lines (i.e., row lines) of the liquid crystal matrix, which are sequentially driven with a shift register.
FIG. 1 is a block diagram showing schematically the configuration of a conventional 4-phase shift register. The shift register of FIG. 1 includes n stages 121 to 12n which are cascade-connected to each other and connected respectively to n row lines ROW1 to ROWn through output lines 141 to 14n. In the shift register, a start pulse SP is input to the first stage 121. The second to nth stages 122 to 12n each respond to an output signal gl to gnxe2x88x921 of a previous stage 121 to 12nxe2x88x921 and two of four clock signals C1 to C4 select the row line ROWi connected to the pixel row. Each of the stages 121 to 12n has the same circuit configuration and shifts the start pulse toward a respective output line 14i every period of the horizontal synchronous signal.
Referring to FIG. 2, there is illustrated a circuit configuration of an arbitrary stage 12i shown in FIG. 1. The stage 12i includes a fifth NMOS transistor T5 for applying a high logic voltage signal to the output line 14i and a sixth NMOS transistor T6 for supplying a low logic voltage signal to the output line 14i.
If an output signal gixe2x88x921 of a previous stage, which is used as the start pulse, goes to a high logic level in the interval t1 as shown in FIG. 3, first and fourth NMOS transistors T1 and T4 are turned-on. Then, a voltage signal VP1 is charged on a first node P1 while a voltage signal VP2 on a second node P2 is discharged. Therefore, the fifth NMOS transistor T5 is turned-on by the voltage VP1 on the first node P1. At this time, since a first clock signal C1 applied to the fifth NMOS transistor T5 has a low logic level, there is developed an output signal Vout having the low logic level on the output line 14i. In the interval t2, when the output signal gixe2x88x921 of the previous stage is inverted to a low logic level and the first clock signal C1 has a high logic level, the first NMOS transistor T1 is turned-off and the voltage signal VP1 on the first node P1 is bootstrapped by coupling with a parasitic capacitor Cgs between the gate and source electrodes of the fifth NMOS transistor T5. To this end, the first clock signal C1 having a high logic level is applied to the output line 14i without a leakage. Next, if the first clock signal C1 changes to a low logic level in the interval t3, the output signal Vout on the output line 14i changes to a low logic level because the fifth NMOS transistor T5 maintains the turned-on state. Finally, in the interval t4 when a third clock signal C3 having a high logic level is applied to a third NMOS transistor T3, the third NMOS transistor T3 is turned-on to charge a high level voltage VDD on the second node P2, thereby developing a high logic level on the second node P2. The voltage signal VP2 charged on the second node P2 allows the sixth NMOS transistor T6 to be turned-on such that the voltage charged on the output line 14i is discharged to a ground voltage source VSS through the sixth NMOS transistor T6. Also, the voltage signal VP2 charged on the second node P2 enables the second NMOS transistor T2 to be turned-on, thereby discharging the voltage signal VP1 charged on the first node P1 toward the ground voltage source VSS through the second NMOS transistor T2.
In FIG. 2, the voltage signal VP1 on the first node P1 is bootstrapped to a very high level in the interval t2 causing the bootstrapping operation. However, if the absolute threshold voltage |Vth| of the first and second NMOS transistors T1 and T2 is low, the voltage signal VP1 on the first node P1 is discharged as shown in FIG. 4. This results from a current signal on the first node P1 leaking through each of the first and second NMOS transistors T1 and T2.
FIG. 4 shows results of a simulation for the prior shift register circuit including transistors for which the absolute threshold voltage |Vth| is low. Also, FIG. 4 shows the waveforms of an output signal Vout of the present stage 12i, and the voltage signals VP1 and VP2 on the first and second nodes P1 and P2. Referring to FIG. 4, the voltage signal VP1 on the first node P1 is distorted by a current signal leaked through each of the first and second NMOS transistors T1 and T2. Due to this, the output signal Vout charged on the output line 14i is also distorted. As a result, it provides a disadvantage in that a next stage malfunctions. Also, the voltage signal VP2 on the second node P2 is unstable because of a current signal leaked by the third and fourth NMOS transistors T3 and T4, as shown in FIG. 4. Due to this, the second and sixth NMOS transistors T2 and T6 also malfunction. Further, since the drain and gate electrodes of the first NMOS transistor T1 are connected to each other, the output signal gixe2x88x921 of the previous stage is dropped down by the threshold voltage Vth of the first NMOS transistor T1 before being applied to the first node P1. The output signal gixe2x88x921 of the previous stage drops down more in the case that it is defective in the liquid crystal panel. In this case, the output signal gixe2x88x921 of the previous stage drops down more and more with each succeeding stage until the last stage. As a result, the shift register circuit does not operate.
Accordingly, it is an object of the present invention to provide a shift register that is capable of increasing the range of operating voltage as well as preventing a malfunction.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to achieve these and other objects of the invention, a shift register according to one aspect includes a plurality of stages which are commonly connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator; which are connected to row lines; and which are connected, in cascade, with respect to a scanning signal, for charging and discharging the row lines.
Each of the plurality of stages included in the shift register according to another aspect comprises: a pull-up transistor having a control electrode and a conduction path connected between the first clock signal line and the output terminal; a pull-down transistor having a control electrode and a conduction path connected between the low level voltage line and the output terminal; first and second transistors having conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor, and each having a control electrode, connected commonly to the second clock signal line, the first and second transistors allowing a voltage to be charged on the control electrode of the pull-up transistor; and third and fourth transistors having conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor, and each having a control electrode, connected commonly to the third clock signal line, the third and fourth transistors allowing a voltage to be charged on the control electrode of the pull-down transistor.
Each of the plurality of stages included in the shift register according to still another aspect comprises: a pull-up transistor having a control electrode and conduction path connected between the first clock signal line and the output terminal; a pull-down transistor having a control electrode and a conduction path connected between the low level voltage line and the output terminal; first and second transistors having conduction paths connected in series between the input terminal and, the control electrode of the pull-up transistor and, each having a control electrode connected, respectively, to the input terminal and the second clock signal line, the first and second transistors allowing a voltage to be charged on the control electrode of the pull-up transistor; and third and fourth transistors having conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor, and each having a control electrode, connected commonly to the third clock signal line, the third and fourth transistors allowing a voltage to be charged on the control electrode of the pull-down transistor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.